Apparatus and method for performing recovery operation of memory system

ABSTRACT

A method for operating a memory system includes performing a block access task on a first block in a memory device, the memory device having a plurality of blocks, generating log information when a power supply voltage becomes lower than a given level, the log information including a check point and block information, the check point indicating the block access task, the block information indicating a second block, and performing the block access task on the second block indicated in the block information of the log information when the power supply voltage becomes equal to or greater than the given level.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.16/570,614 filed Sep. 13, 2019, and claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2018-0143510 filed on Nov. 20,2018, which is incorporated herein by reference in its entirety.

BACKGROUND

Embodiments relate to a memory system, and more particularly, to amethod and apparatus for performing a recovery operation of a memorysystem due to power supply failure or the like.

The computer environment paradigm has changed to ubiquitous computingsystems that can be used anytime and anywhere. That is, use of portableelectronic devices such as mobile phones, digital cameras, and notebookcomputers has rapidly increased. These portable electronic devicesgenerally use a memory system having one or more memory devices forstoring data. A memory system may be used as a main memory device or anauxiliary memory device of a portable electronic device.

Memory systems provide excellent stability, durability, high informationaccess speed, and low power consumption because they have no movingparts. Examples of memory systems having such advantages includeuniversal serial bus (USB) memory devices, memory cards having variousinterfaces, and solid state drives (SSD).

A memory system is provided power from a power supply device. Due to asudden power-off (SPO) of the power supply device, the memory system maybe seriously damaged. For example, when a flash translation layer (FTL)of a memory system includes logics which need to sequentially accessblocks such as a whole memory error-scan, such logics are implemented torecord the last accessed block and then access the next block. However,in an environment where an SPO event frequently occurs, the memorysystem may be powered off and powered on to access a specific block.Then, when the memory system is powered off and powered on, the memorysystem may access the specific block again and this can cause problemsin the memory system.

SUMMARY

Embodiments are directed to a memory system, a data processing system,and an operating method thereof, which can minimize the complexity andperformance degradation of the memory system, maximize the useefficiency of a memory device, and rapidly and stably process data inthe memory device.

Embodiments are directed to a method and apparatus for performing arecovery operation of a memory system by setting a check point for anevent requiring a block access in log information/history informationand randomizing a block to be accessed when the event has not beencompleted, thereby reducing or avoiding repeated access to a specificblock during the recovery operation, when power supply failure occursrepeatedly in the memory system.

Embodiments are directed to a method and apparatus which can blockrepeated access to a specific block in an operation environment of amemory system where a recovery operation may frequently occur, therebyimproving the durability of the memory system and increasing thestability of the recovery operation.

The present disclosure is not limited to the advantages listed above.One skilled in the art would realize other advantages based on thedisclosure herein.

In accordance with an embodiment of the present invention, a method foroperating a memory system includes: performing a block access task on afirst block in a memory device, the memory device having a plurality ofblocks; generating log information when a power supply voltage becomeslower than a given level, the log information including a check pointand block information, the check point indicating the block access task,the block information indicating a second block; and performing theblock access task on the second block indicated in the block informationof the log information when the power supply voltage becomes equal to orgreater than the given level.

In accordance with another embodiment of the present invention, a memorysystem includes: a memory device including a plurality of blocks; and acontroller configured to: performing a block access task on a firstblock in the memory device; generating log information when a powersupply voltage becomes lower than a given level, the log informationincluding a check point and block information, the check pointindicating the block access task, the block information indicating asecond block; and performing the block access task on the second blockindicated in the block information of the log information when the powersupply voltage becomes equal to or greater than the given level.

In accordance with still another embodiment of the present invention, amethod for operating a memory system includes: performing a block accessoperation on a first block in a memory device, the memory deviceincluding a plurality of blocks; accessing log information after anoccurrence of a sudden power-off (SPO) event, the log informationincluding a check point; and continuing the block access operation on asecond block different from the first block when the check point of thelog information indicates that the block access operation was notcompleted for the first block.

BRIEF DESCRIPTION OF THE DRAWINGS

The description herein makes reference to the accompanying drawingswherein like reference numerals refer to like parts throughout theseveral views, and wherein:

FIG. 1 illustrates a data processing system in accordance with anembodiment;

FIG. 2 illustrates a memory system for performing an SPO recoveryprocedure in accordance with an embodiment;

FIG. 3 illustrates a recovery preparation operation of a memory systemin accordance with an embodiment;

FIG. 4 illustrates a recovery operation of a memory system in accordancewith an embodiment;

FIGS. 5A and 5B illustrate examples of a file system used in a memorysystem;

FIG. 6 illustrates a method for generating log information in accordancewith an embodiment;

FIG. 7 illustrates a method for generating log information in accordancewith an embodiment;

FIG. 8 illustrates a recovery process for a memory system in accordancewith an embodiment;

FIG. 9 illustrates a method for processing a block access operation inaccordance with an embodiment; and

FIG. 10 illustrates a method for performing a recovery operation inaccordance with an embodiment.

DETAILED DESCRIPTION

Hereafter, exemplary embodiments of the present invention will bedescribed with reference to the accompanying drawings. It should beunderstood that the following descriptions will be focused on portionsrequired for understanding an operation in accordance with anembodiment, and descriptions of the other portions will be ruled out inorder not to unnecessarily obscure subject matters of the presentdisclosure.

Hereafter, exemplary embodiments will be described in detail withreference to the accompanying drawings.

FIG. 1 illustrates a data processing system 100 in accordance with thepresent embodiment. The data processing system 100 may include a host102 and a memory system 110.

The host 102 may include any of portable electronic devices such as amobile phone, an MP3 player, a laptop computer, and so on, or any ofelectronic devices such as a desktop computer, a game machine, a TV, aprojector, and so on. That is, the host 102 may include a wireless/wiredelectronic device.

The host 102 may include one or more operating systems (OSs). The OSsmay manage and control overall functions and operations of the host 102,and provide an interactive operation between the host 102 and a user whouses the data processing system 100 or the memory system 110. The OSsmay support functions and operations corresponding to the intended useof the user.

For example, the OSs may include a general OS and a mobile OS dependingon the mobility of the host 102. The general OS may include a personalOS and an industrial OS depending on the use environment of the user.For example, the personal OS is specialized to support a serviceproviding function for general users, and may include Windows, Chrome,and the like. The industrial OS is specialized to secure and supporthigh performance, and may include Windows Server, Linux, Unix, and thelike. The mobile OS is specialized to support a mobile service providingfunction and a system power-saving function for users, and may includeAndroid, iOS, Windows Mobile, and the like.

In this embodiment, the host 102 may include a plurality of OSs, andexecute an OS to perform an operation with the memory system 110according to a user's request. The host 102 may transfer a plurality ofrequests corresponding to the user's request to the memory system 110,and thus the memory system 110 may perform operations corresponding tothe requests, i.e., operations corresponding to the user's request.

The memory system 110 may operate in response to a request from the host102. In particular, the memory system 110 may store data accessed by thehost 102. In other words, the memory system 110 may be used as a mainmemory device or a secondary memory device of the host 102.

The memory system 110 may be implemented as any one of various types ofstorage devices, according to a host interface protocol corresponding tothe host 102. The various types of storage devices may include a solidstate drive (SSD), a multi media card (MMC) such as an embedded MMC(eMMC), a reduced size MMC (RS-MMC), or a micro-MMC, a secure digital(SD) card such as a mini-SD or a micro-SD, a universal storage bus (USB)storage device, a universal flash storage (UFS) device, a compact flash(CF) card, a smart media card a memory stick, and so on.

The storage devices for implementing the memory system 110 may includevolatile memory devices and nonvolatile memory devices. The volatilememory devices may include a dynamic random access memory (DRAM), astatic RAM (SRAM), and so on. The nonvolatile memory devices may includea read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM),an erasable programmable ROM (EPROM), an electrically erasableprogrammable ROM (EEPROM), a ferromagnetic RAM (FRAM), a phase-changeRAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a flashmemory, and so on.

The memory system 110 may include a memory device 150 for storing dataaccessed by the host 102 and a controller 130 for controlling datainput/output operations of the memory device 150.

For example, the controller 130 and the memory device 150 may beintegrated into one semiconductor device. For example, the controller130 and the memory device 150 may be integrated into one semiconductordevice to constitute an SSD. When the memory system 110 is used as theSSD, an operating speed of the host 102 coupled to the memory system 110may be further improved.

For another example, the controller 130 and the memory device 150 may beintegrated into one semiconductor device to constitute a memory card.For example, the controller 130 and the memory device 150 may constitutea memory card such as a personal computer memory card internationalassociation (PCMCIA) card, a compact flash (CF) card, a smart media (SM)card, a memory stick, a multimedia card (MMC) such as an RS-MMC or amicro-MMC, an SD card such as a mini-D, a micro-SD, or an SDHC, or auniversal flash storage (UFS) device.

For still another example, the memory system 110 may constitute acomputer, a ultra mobile PC (UMPC), a workstation, a net-book, apersonal digital assistant (PDA), a portable computer, a web tablet, atablet computer, a wireless phone, a mobile phone, a smart phone, ane-book, a portable multimedia player (PMP), a potable game machine, anavigation system, a black box, a digital camera, a digital multimediabroadcasting (DMB) player, a 3-dimensional television, a smarttelevision, a digital audio recorder, a digital audio player, a digitalpicture recorder, a digital picture player, a digital video recorder, adigital video player, a storage constituting a data center, a devicecapable of transmitting/receiving information in a wireless environment,one of various electronic devices constituting a home network, one ofvarious electronic devices constituting a computer network, one ofvarious electronic devices constituting a telematics network, a radiofrequency identification (RFID) device, one of various componentsconstituting a computing system, or the like.

The memory device 150 in the memory system 110 may retain data storedtherein even though no power is supplied. In particular, the memorydevice 150 may store data provided from the host 102 by performing awrite or program operation, and provide data stored therein to the host102 by performing a read operation. The memory device 150 may include aplurality of blocks 152, 154, and 156, each of the blocks 152, 154, and156 may include a plurality of pages, and each of the pages may includea plurality of memory cells coupled to a corresponding one of aplurality of word lines.

In an embodiment, the memory device 150 may include a plurality ofmemory dies each including a plurality of planes. Each of the pluralityof planes may include a plurality of blocks.

The memory device 150 may include a nonvolatile memory device, forexample, a flash memory. The flash memory may have a two-dimensional(2D) or three-dimensional (3D) stack structure.

The controller 130 in the memory system 110 may control the memorydevice 150 in response to a request from the host 102. For example, thecontroller 130 may provide data read from the memory device 150 to thehost 102 in response to a read request, and write data provided from thehost 102 in the memory device 150 in response to a write request. Forthis purpose, the controller 130 may control read, write (or program),and erase operations of the memory device 150.

More specifically, the controller 130 may include a host interface (I/F)132, a processor 134, an error correction code (ECC) unit 138, a powermanagement unit (PMU) 140, a memory I/F 142, and a memory 144.

The host I/F 132 may process a request and data from the host 102, andcommunicate with the host 102 through one or more of various interfaceprotocols such as USB, MMC, PCI-E (Peripheral ComponentInterconnect-Express), SAS (Serial-attached SCSI), SATA (Serial AdvancedTechnology Attachment), PATA (Parallel Advanced Technology Attachment),SCSI (Small Computer System Interface), ESDI (Enhanced Small DiskInterface), IDE (Integrated Drive Electronics), MIPI (Mobile IndustryProcessor Interface), and so on. The host I/F 132 may exchange data withthe host 102 and may be driven by firmware that is referred to as a hostinterface layer (HIL).

The ECC unit 138 may perform an error correction operation, and includean ECC encoder and an ECC decoder. The ECC encoder may generate datawith a parity bit by performing error correction encoding on write datato be programmed to the memory device 150, and the data with the paritybit may be stored in the memory device 150.

When data stored in the memory device 150 is read, the ECC decoder maydetect and correct an error contained in the data read from the memorydevice 150. In other words, the ECC unit 138 may perform errorcorrection decoding on the data read from the memory device 150,determine whether the error correction decoding is successfullyperformed, output an indication signal, for example, an error correctionsuccess/fail signal according to the determination result, and correcterror bits in the read data using a parity bit generated in the errorcorrection encoding process. At this time, when the number of error bitsincluded in the read data is greater than a threshold value thatcorresponds to the number of correctable error bits, the ECC unit 138cannot correct the error bits, and thus outputs the error correctionfail signal indicating that the ECC unit 138 failed to correct the errorbits.

The ECC unit 138 may perform the error correction operation using one ormore of a low density parity check (LDPC) code, a Bose, Chaudhri,Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolutioncode, a recursive systematic code (RSC), and coded modulation such astrellis-coded modulation (TCM) or block coded modulation (BCM). However,embodiments are not limited thereto. The ECC unit 138 may include allcircuits, modules, systems, or devices for performing the errorcorrection operation.

The PMU 140 may provide and manage power for driving the controller 130.That is, the PMU 140 may provide and manage power for driving thecomponents included in the controller 130. The PMU 140 may include apower detector to recognize a state of power applied to the memorysystem 110, for example, a power-on state, a power-off state, or thelike. The power detector may generate an internal control signalcorresponding to the power state.

The memory I/F 142 may serve as a memory/storage I/F to provide aninterface between the controller 130 and the memory device 150, suchthat the controller 130 controls the memory device 150 in response to arequest from the host 102. When the memory device 150 includes a flashmemory, for example, a NAND flash memory, the memory I/F 142 may serveas a NAND flash controller (NFC) The memory I/F 142 may generate acontrol signal for controlling the memory device 150 and process data ofthe memory device 150 under control of the processor 134. The memory I/F142 may be driven by firmware that is referred to as a flash interfacelayer (FIL).

The memory 144 may serve as a working memory of the memory system 110and the controller 130, and store data for driving the memory system 110and the controller 130. More specifically, when the controller 130controls the memory device 150 in response to a request from the host102, for example, when the controller 130 controls read, write (orprogram), and erase operations of the memory device 150 in order toprovide data read from the memory device 150 to the host 102 and towrite data provided from the host 102 in the memory device 150, thememory 144 may temporarily store the read data and the write data toperform such operations on the memory system 110.

The memory 144 may be implemented with a volatile memory. For example,the memory 144 may include a static random access memory (SRAM), adynamic random access memory (DRAM), or the like. As illustrated in FIG.1, the memory 144 may be disposed in the controller 130. However, inanother embodiment, the memory 144 may be implemented as an externalvolatile memory that is disposed outside the controller 130, and thecontroller 130 may have a memory interface for transferring data betweenthe external volatile memory and the controller 130.

As described above, the memory 144 may store data required forperforming a write/read operation between the host 102 and the memorydevice 150. In order to store such data, the memory 144 may include aprogram memory, a data memory, a write buffer/cache, a readbuffer/cache, a data buffer/cache, a map buffer/cache, and the like.

The processor 134 may control overall operations of the memory system110. For example, the processor 134 may control a write (or program)operation or a read operation on the memory device 150 in response to awrite request or read request from the host 102, respectively. Theprocessor 134 may use firmware to control the overall operations of thememory system 110. The processor 134 may be implemented as amicroprocessor or a central processing unit (CPU).

The controller 130 may perform an operation requested by the host 102 inthe memory device 150 using the processor 134. In other words, thecontroller 130 may perform an operation corresponding to a request fromthe host 102 with the memory device 150. In this case, the controller130 may perform a foreground operation corresponding to the request fromthe host 102, for example, a write (or program) operation correspondingto a write request, a read operation corresponding to a read request, anerase operation corresponding to an erase request, or a parameter setoperation corresponding to a set parameter command or set featurecommand as a set request.

The controller 130 may also perform a background operation on the memorydevice 150 using the processor 134. The background operation may includea garbage collection (GC) operation of copying data stored in anarbitrary block among the blocks 152, 154, and 156 of the memory device150 into another arbitrary block, a wear leveling (WL) operation ofswapping the blocks 152, 154, and 156 of the memory device 150 or datastored in the blocks 152, 154, and 156, a map flush operation of storingmap data stored in the controller 130 into the blocks 152, 154, and 156of the memory device 150, or a bad block management operation ofchecking and processing a bad block in the memory device 150.

In an embodiment, the controller 130 may also perform a recoveryoperation of the memory system 110 when a power supply is unstable.

When the power supply is suddenly cut off, i.e., when a sudden power-off(SPO) event occurs, the controller 130 may perform a recover preparationprocess to generate and save log/history information (referred to as“log information” herein) in the memory device 150. When power issupplied again, the controller 130 may perform a recovery process basedon the log information loaded from the memory device 150.

FIG. 2 illustrates a memory system 110 for performing a recoveryoperation in accordance with an embodiment. The memory system 110 mayinclude a controller 130 and a memory device 150. The memory system 110of FIG. 2 may be described with further reference to FIG. 1.

The memory device 150 may include a plurality of blocks 152, 154, and156. The plurality of blocks 152, 154, and 156 may have a structure inwhich a plurality of memory cells are coupled through word lines, bitlines, and the like.

When the plurality of blocks 152, 154, and 156 within the memory device150 are implemented as nonvolatile memories. The plurality ofnonvolatile blocks 152, 154, and 156 may be divided into a plurality ofareas. For example, the memory device 150 may be divided into a systemarea for storing system information and a data area for storing userdata. The system area may not be allowed for a user to access. Thesystem area may store the system information that includes firmware, mapinformation, log information, and the like. On the other hand, the dataarea may store user data inputted/outputted by the user.

In an embodiment, the log information stored in the system area may bestored at a random location among the plurality of blocks 152, 154, and156. However, the user data stored in the data area may be sequentiallystored in the plurality of nonvolatile blocks 152, 154, and 156. Thesystem area and the data area may be controlled in different manners,and neither be used together nor overlap each other.

The controller 130 may perform a write (or program) operation forstoring new data in the memory device 150, or an operation for readingor erasing data stored in the memory device 150. In addition to generaloperations such as the read, erase, and write operations, the controller130 may monitor power applied to the memory system 110, and perform arecovery operation according to the power monitoring result when thepower supply to the memory system 110 is unstable.

In order to perform the recovery operation, the controller 130 mayinclude a power detector 141, a backup unit 135, a processing unit 136,and a recovery unit 137.

As illustrated in FIG. 1, when the controller 130 includes the processor134 and the power management unit 140, the power detector 141 may beincluded in the power management unit 140, and the backup unit 135, theprocessing unit 136, and the recovery unit 137 may be implemented by theprocessor 134. However, embodiments are not limited thereto.

In another embodiment, the backup unit 135 and the recovery unit 137 maybe implemented as logic circuits or program algorithms. For example,when the backup unit 135 and the recovery unit 137 are implemented asthe program algorithms, the backup unit 135 and the recovery unit 137may be included in system firmware.

In another embodiment, the power detector 141 may be disposed outsidethe controller 130.

In an embodiment, the power detector 141 may monitor whether the powersupplied to the controller 130 has a level that is lower than a givenlevel. The given level may correspond to a minimum level at which thememory system 110 stably operates.

When the power is stably supplied to the memory system 110 and thus thesupplied power becomes equal to or higher than the given level, thepower detector 141 may determine that the supplied power is in a stablestate and output a power detection signal PWR indicating a normal powerstate NORMAL_POWER. On the other hand, when the supplied power has alower level than the given level or no power is supplied, the powerdetector 316 may determine that the supplied power is in a unstablestate and output the power detection signal PWR indicating an abnormalpower state LOW_POWER.

When the power is stably supplied to the memory system 110, a request,data, and the like are transferred to the memory system 110 from anotherdevice, for example, the host 102. However, the power supplied to thememory system 110 is suddenly cut off or unstable, the memory system 110cannot perform a normal operation. For example, when the SPO eventoccurs while the memory system 110 performs an operation correspondingto the request, data, and the like, the operation may be stopped beforebeing completed.

Therefore, in order to enhance reliability in interworking with anotherdevice, when power is supplied again, the memory system 110 shouldreturn to a previous condition before an occurrence of the SPO event.

In order to return to the previous condition, the memory system 110 maygenerate and store log information in the memory device 150 when the SPOevent occurs, thereby performing a recovery process when power issupplied again.

The log information may include a plurality of events stored in a datastructure such as a queue. The plurality of events are sequentiallysorted or arranged events that are transferred within a preset timerange before the SPO event occurs. The plurality of events may includetasks which were in progress and tasks which are to be performed laterwhen the SPO event occurred. Furthermore, the plurality of events mayinclude tasks which have not reported yet even though the tasks havebeen already completed. The reporting of the completion of the tasks maybe provided to another device, e.g., the host 102.

The log information may be generated by the backup unit 135. Forexample, when receiving the power detection signal PWR indicating theabnormal power state LOW_POWER from the power detector 141, the backupunit 135 may generate the log information using electrical energy storedin an auxiliary power device (not shown). In an embodiment, theauxiliary power device may include a capacitor capable of storing aminimum amount of electrical energy required for driving the backup unit135 and the processing unit 136 to perform the recovery preparationprocess. In an embodiment, the auxiliary power device is disposed insideor outside the controller 130.

When the backup unit 135 generates the log information, the processingunit 136 may store the log information in the memory device 150. Afterthe processing unit 136 stores the log information in the memory device150, a power state of the memory system 110 may be switched to apower-off state.

When the power is supplied again after the power supply was cut off, thecontroller 130 may load the system information such as firmware or mapinformation, stored in the memory device 150, to a memory (notillustrated) in the controller 130, and then load the log information tothe memory, the log information having been stored when the power supplywas cut off.

For example, when the power state of the memory system 110 is switchedto a power-on state from the power-off state, the recovery unit 137 mayload the log information stored in the memory device 150 to the memorythrough the processing unit 136. The processing unit 136 maysequentially perform the events stored in the log information, so thatthe memory system 110 returns to the previous condition before theoccurrence of the SPO event.

The operations of the backup unit 135 and the recovery unit 137 may beautomatically performed whenever an operation of the memory system 110abnormally ends due to the power supply failure. When the power supplyis cut off after the memory system 110 normally completes all eventscorresponding to a request from the host 102, the recovery unit 137 maynot need to perform the recovery process.

When power is unstably supplied in the operational environment of thememory system 110, e.g., when a power supply unit abnormally operates ina computing device having the memory system 110 mounted therein or powersupplied to the computing device is unstable, the memory system 110 mayrepeatedly perform the recovery operation whenever the power is off andon repeatedly.

The recovery process may include performing the events included in thelog information. When the recovery process is repeated, the same tasksincluded in the events may be repeatedly performed. The repetition ofthe same tasks may not cause a problem in the memory system 110.However, when the tasks included in the log information require accessto a specific block within the memory device 150, the specific block maybe repeatedly accessed when the recovery process is repeated. That is,when the recovery process is repeated due to the power supply failure,access to the specific block may be repeated. As a result, properties ofthe specific block, such as a read count and an erase count, may bedegraded.

Therefore, in order to avoid the repeated access to the specific blockwithin the memory device 150, additional information may be contained inthe log information. For example, when the tasks included in the loginformation include a task required to access a block within the memorydevice 150, the backup unit 135 may insert check points CP at before andafter the corresponding task that is referred to as a “block accesstask.”

The check point CP may be associated with block information indicating ablock that is being accessed before the power supply is cut off. Thebackup unit 135 may store information on a randomly decided block as theblock information. The block information may be included in the loginformation.

The recovery unit 137 performing the recovery process may access therandomly decided block within the memory device 150 based on the blockinformation. Since the block used in the recovery process is randomlydecided whenever the recovery operation is performed, repeated access tothe same block may be avoided even though the same task is repeatedlyperformed when the recovery process is performed.

For example, when it is assumed that the log information includes afirst task of performing a test read on one block among first to tenthblocks within the memory device 150 and the first task has been normallycompleted, the block information may indicate the next block that is tobe accessed in the recovery process.

For example, when the test read has been normally completed on the thirdblock through the first task, the block information may indicate thefourth block on which the next test read operation is to be performed inthe recovery process. On the other hand, when power is unstable or thepower supply is cut off while the first task is performed, the firsttask may not be normally completed on the third block. In this case, thebackup unit 135 may insert check points at before and after the firsttask, and randomly select one of the first to tenth blocks in order togenerate the block information. That is, the backup unit 135 randomizesthe block information. In an embodiment, the backup unit 135 mayrandomly select one of the first, second, and fourth to tenth blocksexcept the third block.

Since the first task included in the log information includes accessinga block within the memory device 150, the check points may be located atbefore and after the first task. During the recovery process, therecovery unit 137 may check the check points in the log information,access the block information, and perform a normal operation on theblock indicated by the block information through the processing unit136.

The test read operation has been exemplified, but various operations mayrequire access to a block in the memory device 150. Examples of thevarious operations may include a task of allocating a block, a task ofwriting data in a block, a task of reading data stored in a block, atask of erasing data stored in a block, and so on.

FIGS. 3 and 4 are flowcharts illustrating a recovery operation of thememory system 110 of FIG. 2 in accordance with an embodiment.Specifically, FIG. 3 illustrates a recovery preparation process of thememory system 110 when the SPO event occurs, and FIG. 4 illustrates arecovery process of the memory system 110 when power is supplied againand stabilized. The recovery operation may include the recoverypreparation process and the recovery process. The recovery operation ofFIGS. 3 and 4 will be described with reference to FIG. 2.

Referring to FIG. 3, the recovery preparation process of the memorysystem 110 may be performed when the SPO event occurs while the memorysystem 110 performs an operation in response to a request from the host102.

When the SPO event occurs and thus power supplied to the memory system110 falls below a given level, the memory system 110 may check anoperation state of the memory system 110 at S31. At S31, the memorysystem 110 may check whether a task requested by the host 102 has beencompleted or not. When the SPO event occurs, the memory system 110 maycheck an operation state of the task that is in progress, is to beperformed, or are not reported yet even though the task has been alreadycompleted. The reporting of the completion of the task may be providedto the host 102.

In order to guarantee the reliability of the operation, the memorysystem 110 may check whether an error occurred in the task based on thechecked operation state, at S33. The error may include the case in whichthe task has not been completed.

When the task is not completed due to the occurrence of the SPO event,i.e., when there is an error as a result of the checking at S33, thememory system 110 may perform the recovery preparation process at S35.The recovery preparation process may include generating log informationand storing the log information in the memory device 150. When therecovery preparation process is completed, the memory system 110 may beshut down.

When the power supplied to the memory system 110 is normally cut off,there may not be any task which is abnormally ended or not completed.Therefore, when the backup unit 135 checks whether an error occurred atS33, there is no error checked. In this case, the memory system 110 maybe shut down without performing the recovery preparation process.

The recovery preparation process of the memory system 110 is performedto raise the operation reliability, and may be performed by the backupunit 135 and the processing unit 136 of the controller 130 as describedabove with reference to FIG. 2. The details of the recovery preparationprocess will be described later.

Referring to FIG. 4, when stabilized normal power is supplied to thememory system 110, the controller 130 may scan a preset area within thememory device 150 at S41. The preset area may include an area in whichsystem information is stored. In an embodiment, the system informationmay include firmware, map information, log information, and the like.

After scanning the preset area at S41, the memory system 110 may loadthe system information such as the firmware, the map information, andthe log information to a memory within the controller 130. The memorysystem 110 may be driven based on the system information at S43.

In an embodiment, when the memory system 110 normally completed alltasks before the SPO event occurred, there may be no tasks which thememory system 110 needs to recover when the normal power is appliedagain. However, when the memory system 110 stored the log informationgenerated in the recovery preparation process, the memory system 110 mayrecover the log information from the system information at S45. When thelog information is recovered, the memory system 110 may return to anormal condition that is the same as the previous condition before theSPO event occurred, and perform tasks included in the log information.

When the memory system 110 recovers the log information and returns tothe normal condition, the memory system 110 may perform a normaloperation with the host 102 at S47.

In an embodiment, the recovery process of the memory system 110 may beperformed until the memory system 110 can perform the normal operationin a condition where the normal power is supplied. However, when powersupplied to the memory system 110 is still unstable, power may berepeatedly cut off and supplied while the preset area is scanned or thelog information is recovered. In this case, the recovery process of thememory system 110 may be repeatedly performed.

In an embodiment, the recovery process of the memory system 110 may beperformed by the recovery unit 137 and the processing unit 136 of thecontroller 130 as described above with reference to FIG. 2. The detailsof the recovery process will be described later.

In an embodiment, when a task included in the log information wasnormally completed before the SPO event occurred, information on thelastly accessed block before the SPO event occurred may be recorded asthe block information, and the next block is processed when performingthe next normal operation after power is supplied again.

However, in an embodiment, if the task included in the log informationwas in progress when the SPO event occurred, information on a randomlyselected block may be recorded as the block information instead of theinformation on the lastly accessed block during the recovery preparationprocess of the memory system 110.

The memory system 110 may use a file system which is more efficient thanfile systems used in existing computing devices. Examples of the filesystem which can be used in the memory system 110 may include F2FS(Flash-Friendly File System), JFSS, JFSS2, YAFFS, LogFS, AXFS, RFFS(Reliable Flash File System) and the like.

FIG. 5A illustrates a file system structure of the F2FS, and FIG. 5Billustrates a file system structure of the RFFS.

Referring to FIG. 5A, the F2FS may divide the entire memory device intosix areas. For example, the six areas may include a data area, asuperblock area, a segment summary area SSA, a segment information tableSIT, a node address table NAT, and a check point area CP.

The data area may include a plurality of blocks capable of storing userdata. Each of the blocks may be used as a node block or a data block.The node block may include an inode or an index of a data block. Thedata block may include a directory or user data. The node block or thedata block may store nodes or data having different attributes accordingto the attributes (hot, warm, and cold) of the nodes or data.

In an embodiment, each of the blocks in the data area may have a size of4 KB or 8 KB. Furthermore, one section may include a plurality of nodeblocks or a plurality of data blocks, but one section may not includenode blocks and data blocks together.

The superblock area may include basic partition information and basicparameters of the F2FS.

The segment summary area SSA may store summary items indicating ownerinformation of all blocks within the data area, for example, informationon a parent inode and information on child inodes belonging to theparent inode.

The segment information table SIT may include per-segment informationsuch as the number of valid blocks in the data area and bitmapinformation on the validities of all the blocks within the data area.The information included in the segment information table SIT may beused to select a segment from which data are to be erased, during aprocess such as garbage collection, and to identify valid blocks withinthe selected segment.

The node address table NAT may include a block address table for findingall “node blocks” stored in the data area.

The check point area CP may store a file system state, a bitmap forvalid information in the segment information table SIT and the nodeaddress table NAT, a list of orphan inodes that lost their parentinodes, and a summary item of current active segments. Through the checkpoint CP, the F2FS can provide a consistent recovery point when the SPOevent or system collision occurs.

In the F2FS shown in FIG. 5A, the other areas except the data area maybe a system area. Log information stored in the system area may bestored at a random position among a plurality of nonvolatile memoryblocks. However, user data stored in the data area may be sequentiallystored in the plurality of nonvolatile memory blocks. The system areaand the data are may be controlled in different manners, and neither beused together nor overlap each other.

Referring to FIG. 5B, the RFFS may divide the entire memory device intothree areas. For example, the three areas may include a locationinformation area LIA, a location information backup area LIBA, and adata area DA.

The location information area LIA may include a plurality of blocks or aplurality of segments. When power is applied to a memory system or whenthe memory system is interconnected to another device such as a host,the location information area LIA may be first scanned. The locationinformation area LIA may store the latest location information of data.

The location information backup area LIBA may be used when a problemoccurs while the location information area LIA is scanned or read.

The data area DA may include the other areas except the locationinformation area LIA and the location information backup area LIBA. Thedata area DA may be used to store all types of information or data suchas log information, block information, meta data, user data, and so on.

The location information area LIA in the RFFS may be used to record thelocations of various pieces of information or various data. The variouspieces of information or various data themselves may be stored in thedata area. Therefore, even when the SPO event or system collisionoccurs, the locations where the log information and the blockinformation are stored may be stored in the location information areaLIA, but contents of the log information and the block information maybe stored in the data area DA.

In an embodiment, the RFFS shown in FIG. 5B may perform the recoveryprocess more rapidly using special information, e.g., an unmount_flag.When flag information on the log information is set to a first value,e.g., ‘1,’ the memory system may recognize that all tasks were completedbefore the power supply was cut off and thus there are no errors. Inthis case, the memory system may omit the recovery process based on thelog information. On the other hand, when the flag information is set toa second value, e.g., ‘0,’ it may indicate that there are tasks whichwere not completed before the power supply was cut off. In this case,the memory system may perform the recovery process based on the loginformation and the block information.

FIG. 6 illustrates a method for generating log information in relationto tasks which the memory system 110 does not complete when the SPOevent occurs.

While the memory system 110 operates, the controller 130 may have mapinformation, user data, and the like to perform an operation requestedby the host 102. For example, when the controller 130 performs a readoperation in response to a read request from the host 102, thecontroller 130 may use the map information for recognizing a taskcorresponding to the read operation and a physical location of data tobe read. When power supply to the memory system 110 is cut off beforethe read operation is not completed, the task corresponding to the readoperation and the physical location of the data to be read (for example,a physical address) may be included in the log information. After that,when power is supplied to the memory system 110 again, the controller130 may perform the read operation according to the task and thephysical location of the data, which are included in the loginformation. Therefore, the memory system 110 can recover the previouscondition before the power supply was cut off.

For another example, when the controller 130 performs a write operationin response to a write request from the host 102, the controller 130 mayuse a task corresponding to the write operation, user data to be storedin the memory device 150, and a physical location where the user dataare to be written. When the power supply to the memory system 110 is cutoff before the write operation is not completed, the controller 130 mayinclude information related to the write operation in the loginformation.

For example, when it is assumed that four tasks are includes in the loginformation, a second task, e.g., Task 2, among the four tasks in thelog information, may be a task that is required to access a block withinthe memory device 150. When the SPO event occurs, if the second taskTask 2 is not completed, the controller 130 may set check points, e.g.,CP #5 and CP #6, before and after the second task Task 2. Furthermore,the controller 130 may decide information L_S_BLK on the block to beaccessed in response to the check points CP #5 and CP #6. In this case,the block information L_S_BLK is randomly decided. In FIG. 6, a blockBLK16 among a plurality of blocks in the memory device 150 may berandomly selected.

In an embodiment, a range of deciding the randomized block may bechanged in response to a task. For example, a task is for reading andtesting the entire memory device 150, one of the plurality of blocks inthe memory device 150 may be decided as the randomized block. On theother hand, when a task is limited to a preset number of blocks amongthe plurality of blocks in the memory device 150, one of the presetnumber of blocks may be decided as the randomized block.

In an embodiment, when deciding the randomized block, a previouslyselected block may be excluded to avoid repeated access to thepreviously selected block.

FIG. 7 illustrates a method for generating log information in accordancewith an embodiment. The method of FIG. 7 will be described withreference to FIG. 2.

Referring to FIG. 7, when the SPO event occurs and thus the powerdetection signal PWR indicating the abnormal power state LOW_POWER isprovided to the backup unit 135, the backup unit 135 is requested togenerate log information at S71.

At S72, the backup unit 135 checks whether a task or event requiringaccess to a block is included in log information and the task or eventhas not been completed. The task or event requiring the access to theblock may be referred to as a “block access task or event.” In thisembodiment, it is assumed that there is a task that has not beencompleted when the SPO event occurs for illustrative convenience.

At S73, the backup unit 135 inserts check points at before and after theblock access task in the log information.

At S74, the backup unit 135 randomizes a block number corresponding tothe block access task.

At S75, the backup unit 135 generates the log information that includesthe check points and the block information L_S_BLK including therandomized block number. In another embodiment, the log information mayfurther include flag information having 1 bit data as described withreference to FIG. 5B, the flag information representing whether or notall tasks and events have been completed before the power supply was cutoff.

When the SPO event occurs, the log information may include a task orevent that has not been completed, a task or event that is to beperformed, and/or a task or event whose completion is not reported yetto the host 102 even though the task or event has been completed. Thebackup unit 135 inserts check points at before and after a block accesstask or event that has not been completed when the SPO event occurred,among the events or tasks included in the log information.

As described above, the backup unit 135 may determine all the pieces ofthe log information for the recovery operation. After that, at S76, thebackup unit 135. may store the log information at a preset locationwithin the memory device 150 through the processing unit 136.

FIG. 8 illustrates a method for performing a recovery process inaccordance with an embodiment. The method of FIG. 8 will be describedwith reference to FIG. 2.

Referring to FIG. 8, when a normal power is supplied to the memorysystem 110 again and thus the power detection signal PWR indicating thenormal power state NORMAL_POWER is provided to the memory system 110, arecovery process is directed at S81.

At S82, the controller 130 loads system information to a memory withinthe controller 130 to drive the memory system 110. In this embodiment,the system information includes log information. In another embodiment,the log information may be loaded separately from other information ofthe system information.

FIG. 8 illustrates that loading the system information is performedafter directing the recovery process. However, in another embodiment,however, directing the recovery process may be performed after loadingthe system information. Such an order may be changed depending on a filesystem structure or a configuration of the system information.

At S83, the recovery unit 137 checks the log information to find checkpoints. The check points may or may not be inserted into the loginformation. When the check points are found before and after a certaintask or event, block information in the log information may be accessedat S84. A block corresponding to the block information is used as afirst block that the memory system 110 accesses in response to thecertain task or event. The first block which is accessed in response tothe certain task or event may be a randomized block.

At S85, the memory system 110 may perform a normal operation (datainput/output or the like) with another interworking device. When thepower supply is cut off again even though the recovery process is notnormally ended, the memory system 110 may perform the recovery processagain.

FIG. 9 illustrates a method for processing a block access operation inaccordance with an embodiment. The block access operation of FIG. 9 willbe described with reference to the memory system 110 of FIG. 1.

It is assumed that a controller, e.g., the controller 130 of FIG. 1,performs an operation of accessing a block of a memory device, e.g., thememory device 150 of FIG. 1, in response to a request from an externaldevice, e.g., the host 102 of FIG. 1.

At S91, the controller 130 of FIG. 1, determines whether an operationrequested by the host 102 is an operation including accessing the memorydevice 150. Herein, the operation including accessing the memory device150 is referred to as a “block access operation.”

When it is determined that the requested operation is not the blockaccess operation at S91, the procedure ends.

On the other hand, when the requested operation is determined as theblock access operation at S91, the controller 130 selects a startingblock in the memory device 150 to perform the block access operation atS92.

At S93, the controller 130 stores a start check point (CP) in loginformation, and records a block address of the selected block in thememory device 150. The start CP is assigned to the selected block, e.g.,Block X, X being 0 or a positive integer. In this case, the blockaddress of the selected block is a block address X.

In an embodiment, the log information may be stored in a memory of thecontroller 130 and/or the memory device 150.

At S94, the controller 130 performs the block access operation for theBlock X.

After the block access operation for the Block X is completed, at S95,the controller 130 stores an end CP in the log information. The end CPis assigned to the Block X. Therefore, at this point, the loginformation stored in the memory device 150 may include the start CP andthe end CP for the Block X.

Afterwards, at S96, the controller 130 determines whether the blockaccess operation is completed on a predetermined number of blocks onwhich the block access operation is supposed to be performed.

When it is determined that the block access operation is completed onall the predetermined number of blocks, the procedure ends.

On the other hand, when it is determined that the block access operationis not completed on all the predetermined number of blocks, at S97, thecontroller 130 selects a next block, e.g., Block X+1. After that, theprocedure goes back to S93, and the processes S93 to S95 are performedon the Block X+1.

As a result of the processes of S93 to S95 on the Block X+1, a start CPand an end CP assigned to the Block X+1 may be stored in the loginformation, and a block address X+1 of the block X+1 is recorded in thememory device 150.

The right side of FIG. 9 shows log contents sequentially stored in thelog information during the block access operation.

However, during the block access operation described in FIG. 9, if theSPO event occurs during the process S94 of performing the block accessoperation for the selected block, the log information includes a startCP for the selected block only. The last log entry of the loginformation becomes the start CP for the selected block. The last logentry represents the most recent entry of the log information that isentered just before the occurrence of the SPO event.

On the other hand, if the SPO event occurs after the block accessoperation for the selected block is completed, i.e., the SPO eventoccurs after the process S95, the log information may include both thestart CP and an end CP for the selected block. The last log entry of thelog information is the end CP for the selected block.

FIG. 10 illustrates a method for performing a recovery operation inaccordance with an embodiment. The recovery operation of FIG. 10 will bedescribed with reference to the memory system 110 of FIG. 1.

The recovery operation of FIG. 10 is performed when a power is appliedto and turns on the memory system 110 after the occurrence of the SPOevent, and thus is referred to as an “SPO recovery (SPOR).”

At S101, the controller 130 reads the last log entry of the loginformation.

At S102, the controller 130 determines whether or not the last log entryis an end CP for the selected block that was being accessed just beforethe occurrence of the SPO event (e.g., herein referred to as “lastselected block”).

When the last log entry is determined to be the end CP, at S103, thecontroller 130 reads a block address of the last selected block.

At S104, the controller 130 determines a next block address using theread block address to continue the block access operation of FIG. 9. Thelast log entry of the end CP indicates that the block access operationfor the last selected block has been completed, and the block accessoperation should be performed on a next block.

At S105, the controller 130 performs the block access operation on thenext block using its block address, i.e., the next block address.

Referring back to S102, when it is determined that the last log entry isnot the end CP for the last selected block, at S106, the controller 130determines whether or not the last log entry is a start CP for the lastselected block. If it is determined that the last log entry is not thestart CP for the last selected block, at S109, the controller 130performs an operation other than the block access operation. In anembodiment, the other operation is not an operation including accessinga block.

On the other hand, if it is determined that the last log entry is thestart CP for the last selected block, at S107, the controller 130selects a random block address instead of reading the block address ofthe last selected block that is stored in the memory device 150.

Thereafter, at S108, the controller 130 performs the block accessoperation on a block corresponding to the randomly selected blockaddress, i.e., a random block. In an embodiment, the random block isselected from a predetermined number of blocks on which the block accessoperation is supposed to be performed. In an embodiment, the randomblock is different from the last selected block.

The last log entry of the start CP means that the SPO event occurredwhile the block access operation was being performed and before theblock access operation on the last selected block can be completed.Therefore, in this embodiment, when the SPO event repeatedly occurs, thecontroller 130 randomly selects a block that is to be accessed andresumes the block access operation on the randomly selected blockinstead of accessing the last selected block repeatedly.

In the above-described embodiments, when a recovery operation, e.g., anSPOR, is repeatedly performed due to power supply failure, a memorysystem generates a check point and save the check point in a memorydevice, and then access different blocks that are randomly selectedbased on a type of the check point, e.g., a start CP, even though thesame tasks or events corresponding to a specific block to which thecheck point is assigned are repeated. Therefore, although the memorysystem repeatedly performs the recovery operation while the power supplyis unstable, it is possible to avoid wearing of a specific block withinthe memory device.

Since the embodiments can prevent repeated access to a specific blockwhen the recovery operation of the memory system is repeated in anoperation environment where the power supply is unstable, it is possibleto reinforce the stability and reliability of the recovery operation andsuppress an overhead in the recovery operation of the memory system.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

What is claimed is:
 1. A method for operating a memory system, themethod comprising: performing a block access task on a first block in amemory device, the memory device having a plurality of blocks;generating log information when a power supply voltage becomes lowerthan a given level, the log information including a check point andblock information, the check point indicating the block access task, theblock information indicating a second block; and performing the blockaccess task on the second block indicated in the block information ofthe log information when the power supply voltage becomes equal to orgreater than the given level, and wherein the log information furtherincludes flag information representing whether or not all events in thelog information have been completed before the power supply voltagebecomes lower than the given level.
 2. The method of claim 1, whereinthe block access task is not completed with respect to the first blockwhen the log information is generated, wherein the block access task isone of a plurality of events in the log information.
 3. The method ofclaim 2, wherein the second block indicated in the block information israndomly selected from a subset of the plurality of blocks, the subsetbeing determined according to an event corresponding to the block accesstask.
 4. The method of claim 2, wherein the second block being differentfrom the first block.
 5. The method of claim 1, wherein generating thelog information includes: sequentially arranging events transferredwithin a preset time range; checking whether the block access task isincluded in the events; and inserting the check point at before an eventcorresponding to the block access task, or after the event correspondingto the block access task, or both.
 6. The method of claim 1, wherein thesecond block indicated in the block information is randomly selected asa lastly accessed block that is to be accessed first during a recoveryoperation.
 7. The method of claim 1, further comprising: usingelectrical energy stored in an auxiliary power device when the powersupply voltage becomes lower than the given level.
 8. The method ofclaim 1, further comprising: storing the log information in the memorydevice; loading the log information into a memory in a controller whenthe power supply voltage becomes equal to or greater than the givenlevel; and identifying the second block in the memory device using thelog information.
 9. The method of claim 8, further comprising: loadingsystem information including firmware and map information to the memoryof the controller of the memory system.
 10. The method of claim 1,wherein the log information is stored in a first area in the memorydevice that is randomly selected, user data are sequentially stored in asecond area in the memory device, and the first area and the second areaare separate from each other.
 11. A memory system comprising: a memorydevice including a plurality of blocks; and a controller configured to:perform a block access task on a first block in the memory device;generate log information when a power supply voltage becomes lower thana given level, the log information including a check point and blockinformation, the check point indicating the block access task, the blockinformation indicating a second block; and perform the block access taskon the second block indicated in the block information of the loginformation when the power supply voltage becomes equal to or greaterthan the given level, and wherein the log information further includesflag information representing whether or not all events in the loginformation have been completed before the power supply voltage becomeslower than the given level.
 12. The memory system of claim 11, whereinthe block access task is not completed with respect to the first blockwhen the log information is generated, wherein the block access task isone of a plurality of events.
 13. The memory system of claim 12, whereinthe second block indicated in the block information is randomly selectedfrom a subset of the plurality of blocks, the subset being determinedaccording to an event corresponding to the block access task.
 14. Thememory system of claim 12, wherein the second block being different fromthe first block.
 15. A method for operating a memory system, the methodcomprising: performing a block access operation on a first block in amemory device, the memory device including a plurality of blocks;accessing log information after an occurrence of a sudden power-off(SPO) event, the log information including a check point; and continuingthe block access operation on a second block different from the firstblock when the check point of the log information indicates that theblock access operation was not completed for the first block, andwherein the log information further includes flag informationrepresenting whether or not all events in the log information have beencompleted before a power supply voltage becomes lower than a givenlevel.
 16. The method of claim 15, further comprising: selecting a blockaddress of the second block when the check point in the log informationis a start check point, the start check point being the most recententry of the log information.
 17. The method of claim 15, wherein ablock address of the second block is randomly selected as a lastlyaccessed block that is to be accessed first during a recovery operation.18. The method of claim 15, further comprising: continuing the blockaccess operation on a third block different from the first block whenthe log information indicates that the block access operation wascompleted for the first block.
 19. The method of claim 18, wherein thelog information includes an end check point for the first block, the endcheck point being the most recent entry of the log information.
 20. Themethod of claim 15, wherein the log information is generated when theSPO event occurs, the SPO event referring to a state when the powersupply voltage to the memory system becomes lower than the given level,the log information including a check point and block information, thecheck point indicating the block access operation, the block informationindicating the second block, and wherein the block access operation isperformed on the second block when the power supply voltage becomesequal to or greater than the given level.